Tier-2: Kria FPGA Streaming Pipeline & SystemVerilog Assertions (SVA)

Note: The Inventory rectangle box indicates that this Digital Media Course is "Out of Stock". This will change when I finish teaching the course by next weekend (July 19, 2026), which is when the video will be available for download along with a copy of the slides, code, and other digital media.
 
You don't need a physical Kria board or a Jetson Nano to master advanced SOC streaming and verification. You only need the free Vivado version 2025.2 Simulator to participate (download from AMD after creating an account with them).
 
In fact, 70% of an FPGA engineer's time is spent exactly where we will be this weekend: inside the Vivado Simulator (XSIM).
 
This coming weekend, I am running an intensive, 2-day live flash masterclass:
"Bulletproofing FPGA Streaming Pipelines with SystemVerilog Assertions (SVA)."
 
If you want to stop wasting hours debugging waveforms manually and learn to write automated safety nets that top-tier hardware companies look for, this is for you.
 
No hardware required. We will be using Vivado (v2025.2) simulation to model a complete, production-grade architecture: a 640x480 RGB565 camera pattern generator streaming data through AXI interfaces under extreme system congestion.
 
The Schedule:
• Time: Two consecutive Sundays from 9:00 AM – 12:00 PM MT (Mountain Time)

• Part 1 (Sunday, July 12): AXI-Stream handshakes, button de-bounce timing windows, FIFO safety guardrails, and stress-testing logic against random AXI VIP backpressure.

• Part 2 (Sunday, July 19): Video frame boundaries, cycle-by-cycle pixel count tracking (307,200 pixels), and verifying RGB565 color distribution using SVA coverage.
 
Because web platforms charge high processing fees and delay payouts, I am offering a Flash Discount if you register directly today:
 
🟢 Tier 1 (Live Access + Design Code & TB): Only $25 (Instead of $29)
🔵 Tier 2 (Live + Recording + Full Lab Code): Only $60 (Instead of $75)— For working professionals who want the reusable code templates for their daily jobs. See Chapter division below for Video segments. 
 
*Full Lab Code includes: Design Code & TB, Vitis workspace and code, and Linux Userspace and UDP code (Tx Kria & Rx Jetson or any computer).
 
**Please DM on LinkedIn or email me by pushing the envelope on the main page for purchase.
 
Because this is a live, interactive lab session happening this weekend, seats are strictly capped so I can answer questions in the chat.
 
The Weekend Schedule & Video Directory (Tier 2 only)
 
To help you easily search and review these concepts later, our 6-hour bootcamp is structured into modular, 30-to-45-minute focused chapters:
 
PART 1: 1st Sunday (9:00 AM – 12:00 PM MT)
Chapter 1: System Design & Kria-to-Jetson Pipeline Overview
Chapter 2: AXI-Stream Protocol Handshake Logic (tvalid/tready)
Chapter 3: SVA Basics: Immediate vs. Concurrent Assertions
Chapter 4: Creating Interface Guardrails (FIFO & Button De-bounce)
Chapter 5: LAB 1: Stress-testing RTL with Random AXI VIP Backpressure
PART 2: 2nd Consecutive Sunday (9:00 AM – 12:00 PM MT)
Chapter 6: Video Frame Boundary Tracking & Geometry Constraints
Chapter 7: Pixel Count Tracking (Verifying the 307,200 Count)
Chapter 8: Inline Data Verification (RGB565 Red Top vs. Blue Bottom)
Chapter 9: SVA Functional Coverage & Simulation Proof
Chapter 10: LAB 2: The Full Frame Completion Challenge & Wrap-up
 
I will be sending out a follow up email on Friday night with critical access links, schedule, and preparation notes. I will be sending out a copy of these items before Friday as well.
 
Thank you!