High-Performance AXI DMA Design and Verification Using SVA

You don't need a physical Kria board or a Jetson Nano to master advanced SOC streaming and verification. You only need the free Vivado version 2025.2 Simulator to participate (download from AMD after creating an account with them).
 
In fact, 70% of an FPGA engineer's time is spent exactly where you will be with this course: inside the Vivado Simulator (XSIM).
 
If you want to stop wasting hours debugging waveforms manually and learn to write automated safety nets that top-tier hardware companies look for, this is for you.
 
In this course you will be using AMD's Vivado in labs for simulation of a complete, production-grade architecture: a 640x480 RGB565 camera pattern generator streaming data through AXI interfaces.
 
This package is for working professionals who want the reusable code templates for their daily jobs and help boost their career options. See Chapter division below for Video segments. 
 
What You Will Learn
 
After completing this workshop you will be able to:
Develop FPGA-based sensor pipelines using AMD Vivado.
Understand data movement from PL through DMA into DDR memory.
Interface embedded software with programmable logic.
Write immediate and concurrent SystemVerilog assertions.
Debug temporal assertion failures using waveforms and simulation.
Verify timing relationships using temporal operators.
Apply SVA to streaming video interfaces.
Build reusable verification modules for future FPGA projects.
 
*Full Course Digital Media List: Course Videos, PDF of PPT Slides, Vivado Project and Vitis Workspace with working C-Code.
 
To help you easily search and review these concepts, the 6-hour bootcamp is structured into chapters that are approx. 10 to 15 minutes long. Videos are 2.5 hrs and labs (4) make up the remaining time. However, that depends on how much you want to learn about SVA!
 
This isn't one of those slide reading, fill in the blank, type of workshop. Included in the videos are a lot of comments about my experiences, as well as other additional information from a highly experienced and educated engineer (me :) !
 
Lecture and Workshop Lab segments:
Chapter 1: System Design & Kria-to-Jetson Pipeline Overview
Chapter 2: Simulation Time Reduction Techniques
Chapter 3: AXI-STREAM Protocol Handshake Logic (tvalid & tready)
Chapter 4: Starting with a Naive Test Bench
LAB 1: Verify word count of data sent vs data expected.
Chapter 5: Retrofitting SystemVerilog Assertions into Existing FPGA Designs 
Chapter 6: SVA Basics: Immediate vs. Concurrent Assertions
LAB 2: Testing to Better Understanding Assertion Behavior
Chapter 7: Adding Backpressure Testing in TB Code
Chapter 8: Creating Interface Guardrails (FIFO & Button De-bounce)
LAB 3: FIFO Guardrails
Chapter 9: Fault Injection at the Testbench Level
LAB 4: Fault Injection Scenarios
Chapter 10: Verification Case Study #4: Verification Closure with Functional Coverage 
Final Wrapup
 
Thank you!