Building an FPGA SoC to Edge AI via AXI DMA Pipeline
Course Title: Building an FPGA SoC to Edge AI via AXI DMA Pipeline (Jetson + Kria SoC FPGA)
Further description/information can be found on the ZenoRobotics YouTube Channel (about a 3 min. video). https://youtu.be/aqEcMVCcxBs
This course is the baseline for other FPGA SoC to Edge AI products to come. You will learn all you will need to have the required basic understanding for courses, such as the new " Kria FPGA Streaming Pipeline & SystemVerilog Assertions (SVA) ".
Video Duration: 2+ hrs
Agenda
- System overview: FPGA => GPU Full Pipeline
- PS/PL Integrated Hardware Architecture
- Where such hybrid processing technologies accel
- The real challenge
- About DMA
- AXI + DMA data movement (CPU sets control registers).
- AXI Protocol Types
- Common Pitfalls
- Vitis bare-metal C code analysis (test DMA)- "Live" Demo of running C code on Kria Bare-Metal (FPGA) via Vitis
- Linux userspace concept
- UDP concept
- Multi sensor integration architecture example
- Meta data merge
File Structure:
KR260-multisensor-pipeline/
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|__ Video
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|__ README-CourseBundle.pdf
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|__ docs/
| |
| |__ *Slides (FPGA_Advanced_Pipeline.pdf)
| |
| |__ About_the_dts_file.pdf
| |
| |__ *Configure_DMA_Userpace_and_PL.pdf – (Main directions page for Kria userspace creation and use.)
| |
| |__ How_to_load_boot_fw.pdf – (Extra info.)
| |
| |__ JTAG_Boot_Mode_Bare_Metal_Vitis.pdf – (How to put Vitis in JTAG mode.)
| |
| |__ Programs_Startup.pdf
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| |__ UDP_Comm_Setup.pdf
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| __ fpga-vitis
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| |__ kria_orin_proj (Vivado v2025.2)
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| |__ vitis_new_setup (Vitis v2025.2)
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|__ Pico-microPython
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| |__ bno055.py, bno055_base.py, packetize_bno055_quant.py
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|__ kria_overlay_plus (.dts + .dtbo, Kria Userspace C Code)
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| |__ top_kr260_uio.dts, top_kr260_uio.dtbo, and top_kr260_wrapper.bin (Vivado gen.)
| |
| |__ c_programs
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| |__ dma_uio_test (executable), dma_uio_test.c, compile_test (compile script)
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|__ jetson (Python IMU Packet Receiver and Data Converter)
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|__ jetson_udp_rcvr_32bit.py
AMD/Xilinx Vitis and Vivado Versions
The Vivado and Vitis projects were created with AMD/Xilinx verion 2025.2.